rev. d dac10Cspecifications C2C electrical characteristics dac10f dac10g parameter symbol conditions min typ max min typ max units monotonicity 10 10 bits nonlinearity nl 0.3 0.5 0.6 1 lsb differential nonlinearity dnl 0.3 1 0.7 lsb settling time t s all bits switched on or off settle to 0.05% of fs (see note) 85 135 85 150 ns output capacitance c o 18 18 pf propagation delay t plh all bits switched r l = 5 k w 50 50 ns t phl r l = 0 k w 50 50 ns output voltage full-scale current change C5.5 C5.5 v compliance v oc <1 lsb +10 +10 v gain tempco tci fs (see note) 10 25 10 50 ppm/ c full-scale symmetry i fss i fr Ci fr 0.1 4 0.1 4 m a zero-scale current i zs 0.01 0.5 0.01 0.5 m a full-scale current i fr (see note) 3.960 3.996 4.032 3.920 3.996 4.072 ma reference input slew rate di/dt 6 6 ma/ m s reference bias current i b C1 C3 C1 C3 m a power supply pps/ fs + 4.5 v v+ C18 v 0.001 0.01 0.001 0.01 % d i fs /% d v sensitivity pps/ fs C C18 v vC C10 v 0.0012 0.01 0.0012 0.01 % d i fs /% d v power supply current i+ v s = 15 v; i ref = 2 ma 2.3 4 2.3 4 ma iC C9 C15 C9 C15 ma i+ v s = +5 v; C7.5 v; i ref = 1 ma 1.8 4 1.8 4 ma iC C5.9 C9 C5.9 C9 ma power dissipation p d v s = 15 v; i ref = 2 ma 231 285 231 285 mw p d v s = +5 v; C7.5 v; i ref = 1 ma 85 88 85 88 mw logic input levels v il v lc = 0 0.8 0.8 v v ih v lc = 0 2 2 v logic input curr ents i il v lc = 0; v in = 0.8 v C10 C5 C10 C5 m a i ih v in = 2.0 v 0.001 10 0.001 10 m a electrical characteristics dac10f dac10g parameter symbol conditions min typ max min typ max units monotonicity 10 10 bits nonlinearity nl 0.3 0.5 0.6 1 lsb differential nonlinearity dnl 0.3 1 0.7 lsb output voltage compliance v oc full-scale current change, <1 lsb C5 C6/+18 +10 C5 C6/+15 +10 v full-scale current i fs v ref = 10.000 v, r14 = r15 = 5.000 k w 3.978 3.996 4.014 3.956 3.996 4.036 ma full-scale symmetry i fss i fr Ci fr 0.1 4 0.1 0.4 m a zero-scale current i zs 0.01 0.5 0.01 0.5 m a note: guaranteed by design. (@ v s = 6 15 v; i ref = 2 ma; 0 8 c t a +70 8 c for dac10f and g, unless otherwise noted. output characteristics apply to both i out and i out .) (@ v s = 6 15 v; i ref = 2 ma; t a = +25 8 c, unless otherwise noted. output characteristics apply to both i out and i out .)
C3C rev. d dac10 wafer test limits dac10n parameter symbol conditions limit units resolution 10 bits min monotonicity 10 bits min nonlinearity nl 0.5 lsb max output voltage compliance v oc true 1 lsb +10 v max C5 v min output current range i fs 3.996 ma 18 m a max zero-scale current i zs all bits off 0.5 m a max logic input 1 v ih i in = 100 na 2 v min logic input 0 v il v lc @ ground 0.8 v max i in = C100 m a positive supply current i+ v+ = 15 v 4 ma max negative supply current iC v+ = C15 v C15 ma max note: electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard produce dice. typical electrical characteristics dac10f parameter symbol conditions typ units settling time t s to 1/2 lsb when output is switched from 0 to fs 85 ns gain temperature coefficient (tc) v ref tempco excluded 10 ppm fs/ c output capacitance 18 pf output resistance 10 m w (@ v s = 6 15 v, i ref = 2 ma, t a = +25 8 c, unless otherwise noted. output characteristics refer to both i out and i out ). (@ v s = 6 15 v, i ref = 2 ma, unless otherwise noted. output characteristics refer to both i out and i out ). dice characteristics die size 0.091 3 0.087 inch, 7,917 sq. mils (2.311 3 2.210 mm, 5.107 sq. mm)
dac10 C4C rev. d absolute maximum ratings 1 operating temperature DAC10FX, gx, gs, gp . . . . . . . . . . . . . . . . 0 c to +70 c junction temperature (t j ) . . . . . . . . . . . . . C65 c to +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . +300 c v+ supply to vC supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 v logic inputs . . . . . . . . . . . . . . . . . . . . . . vC to vC plus 36 v v lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vC to v+ analog current outputs . . . . . . . . . . . . . . . . +18 v to C18 v reference inputs (v 16 to v 17 ) . . . . . . . . . . . . . . . . . vC to v+ reference input differential voltage (v 16 to v 17 ) . . . . 18 v reference input current (i 16 ) . . . . . . . . . . . . . . . . . . 2.5 ma package type u ja 2 u jc units 18-lead hermetic dip (x) 48 15 c/w 18-lead soic (s) 89 28 c/w 18-lead plastic dip (p) 74 33 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for worst case mounting conditions, i.e., q ja is specified for device in socket for cerdip packages. ordering guide inl temperature package package model (lsb) range description options DAC10FX 0.5 0 c to +70 c cerdip q-18 dac10gx 1 0 c to +70 c cerdip q-18 dac10gs 1 0 c to +70 c soic r-18 dac10gp 1 0 c to +70 c plastic dip n-18 pin connections 18-lead hermetic dip 18-lead plastic dip 18-lead soic top view (not to scale) 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 dac10 b5 b4 v lc i o vC i o b3 b2 (msb) b1 b6 b7 comp v ref (C) v ref (+) v+ b8 b9 b10 (lsb)
caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. basic connections
dac10 C6C rev. d figure 13. offset binary operation figure 12. basic bipolar output operation figure 11. basic unipolar negative operation figure 9. basic negative reference operation figure 10. recommended full-scale adjustment circuit dac10 16 17 r ref r17 4 2 i o i o i fs Cv ref r ref 2 3 Cv ref note: r ref sets i fs ; r17 is for bias current cancellation b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 msb lsb dac10 i ref = 2.000ma 16 2 4 1.25k v 1.25k v i o i o b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 1111 111 111 1000 000 010 1000 000 000 0111 111 111 0000 000 010 0000 000 000 full range half-scale +lsb half-scale half-scale Clsb half-scale +lsb zero scale +lsb i o ma 0.000 1.992 1.996 2.000 3.992 3.996 e o C0.000 C2.490 C2.495 C2.500 C4.990 C4.995 i o ma 3.996 2.004 2.000 1.996 0.004 0.000 e o C4.995 C2.505 C2.500 C2.495 C0.005 0.000 e o e o b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 msb lsb dac10 i ref (+) = 2.000ma 16 2 4 2.5k v i o i o 2.5k v +5v e o e o b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 1111111 111 1111111 101 1000000 010 1000000 000 1111111 111 0000000 010 positive full range positive full range Clsb zero-scale +lsb zero-scale negative full-scale +lsb negative full-scale e o +5.000 +4.990 +0.020 +0.010 0.000 C4.980 e o C4.990 C4.980 C0.010 0.000 +0.010 +4.990 zero-scale Clsb 0000000 000 +5.000 C4.990 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 msb lsb dac10 2 4 2.5k v i o i o +15v e o +15v 2 v in v o ref01 gnd 4 6 5kv 5.000 k v 5kv vC v+ c c v lc C15v b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 1111 111 111 1000 000 000 0000 000 010 0000 000 000 positive full range zero-scale negative full-scale +lsb negative full-scale e o +4.990 0.00 C4.990 C5.000 i ref (+) 2ma dac10 16 17 v ref +10v low t.c. 4.5k v 39kv 10kv pot 1v approximately 5kv
dac10 rev. d C7C figure 15. positive low impedance output operation figure 16. negative low impedance output operation figure 17. interfacing with various logic families figure 14. settling time measurement dac10 e o op01 r l 0 to +i fr 3 r l i o i o 4 2 for complementary output (operation as a negative logic dac), connect inverting input of op amp to i o (pin 2); connect i o (pin 4) to ground. i fr = 1023 1024 3 2 3 i ref dac10 e o op15 0 to Ci fr 3 r l i o i o 4 2 i fr = 1023 1024 3 2 3 i ref for complementary output (operation as a negative logic dac), connect noinverting input of op amp to i o pin 2); connect i o (pin 4) to ground. r l ecl 13kv C5.2v v lc to pin 1 2n3904 "a" 39kv 3kv 6.2k v 2n3904 +15v v lc 9.1k v v th = v lc +1.4v +15v cmos v th = +7.6v 6.2k v 0.1mf dac10 ttl v th = +1.4v v lc 1 51 v 2.5k v 2.5k v 10kv 1m v 1/4w, 5% carbon 2kv 4kv 1kv 499k v 1/4w, 5% carbon 0.01 mf 1mf 0.01 mf 0.1m f10 m f 4.7mf 0.01 mf 1mf 0.01 m f 4.7mf 0.1m f10 m f +15v v l 0.500v 6 0.001v +15v C15v v o C15v +15v 15 16 18 3 17 1 2 5 14 4 2 6 5 4 ref-01 C15v C15v 175mv 2n918 2n918 low-to-high settling v l = 16.500v 6 0.001v high-to-low settling v l = 0.500v 6 0.001v 1/2 lsb settling = 7.8mv notes: 1. case of 2n918s must be grounded. 2. resistors are 1/4w mf, 1% unless otherwise specified. 3. use fet probe (7a11 scope plugin). d.u.t. in5711
dac10 C8C rev. d applications dac10 optional resistor for offset inputs r ref r l r l 2 4 17 16 r p r in +v ref r eq = 800v no cap 0v typical values: r in = 1kv +v in = 2v 1 r in 1 r p 1 r ref + r eq = + 1 figure 18. pulsed reference operation reference amplifier setup the dac10 is a multiplying d/a converter in which the output current is the product of a digital number and the input refer- ence current. the reference current may be fixed or may vary from nearly zero to 2 ma. the full-scale output current is a linear function of the reference current and is given by: i fr = 1023 1024 2 i ref where i ref equals current flowing into pin 16. in positive reference applications, an external positive reference voltage forces current through r16 into the v ref (+) terminal (pin 16) of the reference amplifier. alternatively, a negative reference may be applied to v ref (C) at pin 17; reference current flows from ground through r16 into v(+) as in the positive reference case. this negative reference connection has the ad- vantage of a very high impedance presented at pin 17. r17 (nominally equal to r16) is used to cancel bias current errors; r17 may be eliminated with only a minor increase in error. bipolar references may be accommodated by offsetting v ref or pin 17. the negative common-mode range of the reference amplifier is given by: v cm C = vC plus (i ref 2 k w ) plus 2 v. the positive common-mode range is v+ less 1.8 v. when a dc reference is used, a reference bypass capacitor is recommended. a 5 v ttl logic supply is not recommended as a reference. if a regulated power supply is used as a reference, r16 should be split into two resistors with the junction bypassed to ground with a 0.1 m f capacitor. for most applications, the tight relationship between i ref and i fs will eliminate the need for trimming i ref . if required, full- scale trimming may be accomplished by adjusting the value of r16, or by using a potentiometer for r16. an improved method of full-scale trimming that eliminates potentiometer tc effect is shown in the recommended full-scale adjustment circuit. the reference amplifier must be compensated by using a capaci- tor from pin 18 to vC. for fixed reference operation, a 0.01 m f capacitor is recommended. for variable reference applications, see section entitled reference amplifier compensation for mul- tiplying applications. multiplying operation the dac10 provides excellent multiplying performance with an extremely linear relationship between i fs and i ref over a range of 4 ma to 4 m a. monotonic operation is maintained over a typical range of i ref from 100 m a to 2 ma. reference amplifier compensation for multiplying applications ac reference applications will require the reference amplifier to be compensated using a capacitor from pin 18 to vC. the value of this capacitor depends on the impedance presented to pin 16 for r16 values of 1.0 k w , 2.5 k w and 5.0 k w , minimum values of c c are 15 pf, 37 pf and 75 pf. larger values of r16 require proportionately increased values of c c for proper phase margin. for fastest response to a pulse, low values of r16 enabling small c c values should be used. if pin 16 is driven by a high imped- ance such as a transistor current source, none of the above val- ues will suffice and the amplifier must be heavily compensated, which will decrease overall bandwidth and slew rate. for r16 = 1k w and c c = 15 pf, the reference amplifier slews at 4 ma/ m s enabling a transition from i ref = 0 to i ref = 2 ma in 500 ns. operation with pulse inputs to the reference amplifier may be accommodated by an alternate compensation scheme. this technique provides lowest full-scale transition times. an internal clamp allows quick recovery of the reference amplifier from a cutoff (i ref = 0) condition. full-scale transition (0 ma to 2 ma) occurs in 120 ns when the equivalent impedance at pin 16 is 200 w and c c = 0. this yields a reference slew rate of 16 ma/ m s, which is relatively independent of r in and v in values. logic inputs the dac10 design incorporates a unique logic input circuit that enables direct interface to all popular logic families and provides maximum noise immunity. this feature is made pos- sible by the large input swing capability, 2 m a logic input current and completely adjustable logic threshold voltage. for vC = C15 v, the logic inputs may swing between C5 and +18 v. this enables direct interface with +15 v cmos logic, even when the dac10 is powered from a +5 v supply. minimum input logic swing and minimum logic threshold voltage are given by: vC plus (l ref 2k w ) plus 3 v. the logic threshold may be adjusted over a wide range by placing an appropriate voltage at the logic threshold control pin (pin 1, v lc ). the appropriate graph shows the relationship between v lc and v th over the temperature range, with v th nominally 1.4 v above v lc . for ttl interface, simply ground pin 1. when interfacing ecl, an i ref = 1 ma is recom- mended. for interfacing other logic families, see figure 17. for general setup of the logic control circuit, it should be noted that pin 1 will sink 1.1 ma typical; external circuitry should be de- signed to accommodate this current. fastest settling times are obtained when pin 1 sees a low imped- ance. if pin 1 is connected to a 1 k w divider, for example, it should be bypassed to ground by a 0.01 m f capacitor.
dac10 rev. d C9C analog output currents both true and complemented output sink currents are provided where i o + i o = i fs . current appears at the true output when a 1 is applied to each logic input. as the binary count increases, the sink current at pin 4 increases proportionally, in the fashion of a positive logic d/a converter. when a 0 is applied to any input bit, that current is turned off at pin 4 and turned on at pin 2. a decreasing logic count increases i o as in a negative or inverted logic d/a converter. both outputs may be used simultaneously. if one of the outputs is not required, it must still be connected to ground or to a point capable of sourc- ing i fs . do not leave an unused output pin open. both outputs have an extremely wide voltage compliance en- abling fast direct current-to-voltage conversion through a resis- tor tied to ground or other voltage source. positive compliance is 36 v above vC and is independent of the positive supply. negative compliance is +10 v above vC. the dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. this feature is especially useful in cable driving, crt deflection and in other balanced applications such as driving center-tapped coils and transformers. power supplies the dac10 operates over a wide range of power supply volt- ages from a total supply of 9 v to 36 v. when operating with vC supplies of C10 v or less, i ref 1 ma is recommended. low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range and negative logic threshold range; consult the various figures for guidance. for example, operation at C9 v with i ref = 2 ma is not recom- mended because negative output compliance would be reduced to near zero. operation from lower supplies is possible, however at least 8 v total must be applied to ensure turn-on of the inter- nal bias network. symmetrical supplies are not required, as the dac10 is quite insensitive to variations in supply voltage. battery operation is feasible as no ground connection is required; however, an artifi- cial ground may be used to ensure that logic swings, etc., remain within acceptable limits. temperature performance the nonlinearity and monotonicity specifications of the dac10 are guaranteed to apply over the entire rated operating tempera- ture range. full-scale output current drift is tight, typically +10 ppm/ c, with zero-scale output current and drift essentially negligible compared to 1/2 lsb. the temperature coefficient of the reference resistor, r14, should match and track that of the output resistor for minimum overall full-scale drift. settling times of the dac10 decrease approximately 10% at C55 c; an increase of about 15% is typi- cal at +125 c. settling time the dac10 is capable of extremely fast settling times; typically 85 ns at i ref = 2 ma. judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. the logic switch design enables propagation delays of only 35 ns for each of the 10 bits. settling time to within 1/2 lsb of the lsb is therefore 35 ns, with each progressively larger bit taking successively longer. the msb settles in 85 ns, thus determining the overall settling time of 130 ns. settling to 8-bit accuracy requires about 60 ns to 78 ns. the output capacitance of the dac10, including the package, is approximately 18 pf; therefore, the output rc time constant dominates settling time if r l > 500 w . settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. settling time also remains essentially constant for i ref values down to 1 ma, with gradual increases for lower i ref values. the principal advantage of higher i ref values lies in the ability to attain a given output level with lower load resistors, thus reducing the output rc time constant. measurement of settling time requires the ability to accurately resolve 2 m a; therefore, a 4 k w load is needed to provide ad- equate drive for most oscilloscopes. the settling time fixture of schematic titled settling time measurement uses a cascode design to permit driving a 4 k w load with less than 5 pf of para- sitic capacitance at the measurement node. at i ref values of less than 1 ma, excessive rc damping of the output is difficult to prevent while maintaining adequate sensitivity. however, the major carry from 0111111111 to 1000000000 provides an accu- rate indicator of settling time. this code change does not re- quire the normal 6.2 time constants to settle to within 0.2% of the final value, and thus settling times may be observed at lower values of i ref . dac10 switching transients or glitches are very low and may be further reduced by small capacitive loads at the output with a minor sacrifice in settling time. fastest operation can be obtained by using short leads, minimiz- ing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and v lc terminals. supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 m f capaci- tors at the supply pins provide full transient protection.
dac10 C10C rev. d outline dimensions dimensions shown in inches and (mm). 18-lead cerdip (q-18) 18 1 9 10 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.960 (24.38) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 18-lead plastic dip (n-18) 18 19 10 0.925 (23.49) 0.845 (21.47) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 18-lead wide body sol (r-18) 0.4193 (10.65) 0.3937 (10.00) 18 10 9 1 0.4625 (11.75) 0.4469 (11.35) pin 1 0.2992 (7.60) 0.2914 (7.40) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 c3134C0C5/98 printed in u.s.a.
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